1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to improved methods and systems for polishing a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabrication of an integrated circuit involves numerous processing steps. After implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the implant regions from overlying conducting regions. Interconnect routing is then placed over the interlevel dielectric and connected to the implant regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.
Forming substantially planar upper surfaces of a semiconductor topography during intermediate process steps may facilitate fabrication of layers and structures that meet design specifications. For example, a dielectric layer may be formed across a previously patterned layer of a semiconductor topography using a process such as chemical vapor deposition (xe2x80x9cCVDxe2x80x9d). Elevational disparities of the deposited dielectric layer may be reduced by planarizing the deposited dielectric layer using a process such as chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d). A contact opening may be formed within the planarized dielectric layer and subsequently filled with a layer of conductive material. In this manner, the layer of conductive material may be formed within the contact opening and on an upper surface of the planarized dielectric layer. As such, the layer of conductive material may also be planarized such that an upper surface of the contact structure may be substantially planar with an upper surface of the dielectric layer.
Additional layers and structures may be formed upon the contact structures and the dielectric layer. The additional layers and structures may include, for example, additional dielectric layers, additional contact structures, local interconnect wires, and/or metallization layers. In this manner, the planarized upper surface of the contact structures and the dielectric layer may facilitate the formation of such additional layers and structures having uniform vertical and lateral dimensions. For example, the planarization of the semiconductor topography may facilitate the formation of local interconnect structures having a substantially uniform thickness by providing a planar surface upon which a dielectric material may be deposited to insulate adjacent local interconnect structures. Moreover, the planarization of the semiconductor topography may aid in forming local interconnect structures having uniform lateral dimension by providing a planar surface upon which a patterned masking layer may be formed. In this manner, a masking layer may be accurately patterned by a lithography technique such that the pattern may be accurately transferred to a dielectric layer to form local interconnect structures. Accordingly, layers and structures of a semiconductor device may be formed having dimensions which are approximately equal to the design specifications of the semiconductor device.
Forming a substantially planar upper surface of such layers and structures may play an important role in the functionality of a semiconductor device. For example, problems with step coverage may arise when a dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and recessed regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, substantially planar surfaces may become increasingly important as the feature sizes of semiconductor devices are reduced, since the depth of focus required to pattern an upper surface of a semiconductor topography may increase with reductions in feature size. If a topography is nonplanar, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device. Furthermore, correctly patterning layers upon a topological surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational xe2x80x9chillxe2x80x9d or xe2x80x9cvalleyxe2x80x9d area. The presence of such elevational disparities therefore makes it difficult to print high resolution features.
As mentioned above, CMP is a technique commonly employed to planarize or remove the elevational fluctuations in the surface of a semiconductor topography. A conventional CMP process may involve placing a semiconductor wafer face-down on a polishing pad which lies on or is attached to a rotatable table or platen. A typical polishing pad medium may include polyurethane or polyurethane-impregnated polyester felts. During the CMP process, the polishing pad and the semiconductor wafer may be rotated relative to each other as the wafer is forced against the pad. An abrasive, fluid-based chemical suspension, often referred to as a xe2x80x9cslurry,xe2x80x9d may be deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The rotational movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. In addition, the pad itself may physically remove some material from the surface of the semiconductor topography. Therefore, the process may employ a combination of chemical stripping and mechanical polishing to form a planarized surface.
Unfortunately, a CMP process may not form a substantially planar surface across an entire semiconductor topography. For example, if the polishing rate of CMP varies across a topography, a planarized semiconductor topography may have substantial elevational disparities. Such disparities may be particularly prevalent at an edge of the topography. For example, a thickness of a semiconductor topography may be greater at the edge of the topography than at an inner portion of the topography. The greater thickness of the semiconductor topography at its edge may be due to a slow polish rate at the edge of the topography as compared to polish rates at other regions of the topography. Several factors may influence the polish rates of a CMP process. For example, the polish rates may depend on the surface materials being polished or the rotational and lateral movement of the polishing pad relative to the semiconductor topography. Additional factors which may affect polish rates of the CMP process may include elements such as the polishing tool, the pad materials, the slurry, and interactions between these elements.
Elevational disparities which may be present on a semiconductor topography subsequent to chemical mechanical polishing may inhibit the formation of semiconductor devices on a portion of the semiconductor topography. For example, a thickness of the semiconductor topography may be greater at an outer edge of the semiconductor topography than at an inner portion of the semiconductor topography. As such, the thickness of the semiconductor topography at the outer edge may be outside of design specifications for a semiconductor device. Consequently, semiconductor devices formed at the outer edge of such a semiconductor topography may have dimensions which deviate significantly from design specifications. In this manner, acceptable devices may not be formed on an area of the semiconductor topography having such elevational disparities, thereby reducing the number of devices which may be formed on the semiconductor topography. As such, the presence of such elevational disparities on a semiconductor topography may reduce manufacturing yield and may increase production costs per semiconductor device.
Accordingly, it would be advantageous to develop a method and a system for forming a semiconductor topography having a substantially planar upper surface across the entire semiconductor topography, including its outer edge.
The problems outlined above may be in large part addressed by a method, a wafer carrier, components of a wafer carrier, and a CMP system adapted for processing a semiconductor topography. In particular, a method is provided in which a greater pressure may be applied to a first portion of a semiconductor topography than in a second portion of the topography. As such, the first portion of the topography may be polished at a faster rate than the second portion of the topography. For instance, a portion of an upper layer in a region adjacent to an outer edge of the semiconductor topography may be polished at a faster rate than a portion of the upper layer in a region comprising the center of the topography. Consequently, the method may subsequently provide a manner in which a substantially planar upper surface may be formed across a topography including a region adjacent to an outer edge of the topography. In addition, a system is provided in which a greater pressure may be applied in a first portion of a semiconductor topography than in a second portion of the topography during a polishing process. The first portion may, for example, be adjacent to an outer edge of the topography, while the second portion may include the center of the topography. Alternatively, the first portion and second portion of the topography may each include any region of the topography.
The method preferably includes two steps with which to form a substantially planar surface. For example, the method may include a polish step, which may polish a region adjacent to the outer edge of the topography at a faster rate than a region including the center of the topography. Such a process may be achieved by applying greater pressure at the region adjacent to the outer edge of the topography than a region including the center of the topography. The polish step may compensate for elevational disparities, which may have been formed within an upper layer of a semiconductor topography. Thus, the method may form a substantially planar upper surface across the entirety of the semiconductor topography. The method may also include a planarization step, which may precede or follow the polish step. The planarization step preferably has a substantially different polish rate profile than the polish step. In particular, the planarization step may polish a region adjacent to the outer edge of the topography at a slightly slower rate than a region including the center of the topography. In an embodiment, the planarization step may apply a substantially uniform pressure across the topography to obtain its polish rate profile. In another embodiment, the planarization step may assert a substantially uniform pressure across the topography except in the region adjacent to the outer edge of the topography.
In one embodiment, a CMP system may be adapted to apply a greater pressure in one or more regions of the semiconductor topography as compared to another regions of the topography when the topography is pressed against a polishing pad. The CMP system may include a carrier plate and/or a carrier backing film adapted to apply varying degrees of pressure across a topography. As such, a CMP system may be adapted to apply a greater pressure in a region of a semiconductor topography adjacent its outer edge than in a region comprising the center of the topography. In one embodiment, the region of the topography adjacent to the outer edge may extend inward from the outer edge by an amount between approximately 1 mm and approximately 10 mm. More specifically, the region adjacent to the outer edge of the topography may extend inward from the outer edge by an amount between approximately 2 mm and approximately 4 mm.
A wafer carrier may be adapted to apply a greater pressure in specified regions of the semiconductor topography as compared to other regions of the topography during a polishing process. As with the CMP system, a wafer carrier may include a carrier plate and/or a carrier backing film adapted to apply a greater pressure in a first portion of a semiconductor topography than in a second portion of the topography. In this manner, such a wafer carrier may be included in a CMP system to allow varying degrees of pressure to be applied to the semiconductor topography. The application of pressure within a polishing process is generally dependent upon the interface between the backing film and the semiconductor topography. As such, the CMP system and wafer carrier as described herein allow the carrier backing film to contact at least a portion of the topography during the polishing process. The wafer carrier and/or CMP system may also include a carrier ring configured to hold the semiconductor topography in alignment with the film.
There are several embodiments in which a carrier backing film may be adapted to apply a greater pressure in one or more portions of a semiconductor topography than in other portions of the topography when the topography is pressed against a polishing pad. In particular, a carrier backing film may be adapted to apply a greater pressure in a first portion of a semiconductor topography than in a second portion of the topography when the topography is pressed against a polishing pad. For example, a backing film may be formed such that the lateral dimensions of the film may be approximately equal to lateral dimensions of the first portion of the semiconductor topography. In one embodiment, the first portion may extend inward from an outer edge of the topography by an amount between approximately 1 mm and approximately 10 mm. As such, an outer diameter of the film may be larger than an inner diameter of the film by an amount between approximately 2 mm and approximately 20 mm. Alternatively, the backing film may include a layer of varied thickness. More specifically, a region of the layer corresponding to the first portion of the semiconductor topography may be thicker than a region of the layer corresponding to the second portion of the semiconductor topography. Regions of the backing film corresponding to portions of the semiconductor topography may refer to the mirrored lateral dimensions of the regions and portions of the two components.
A carrier plate may also be adapted to apply a greater pressure in one or more regions of the topography than in other regions of the topography when the topography is pressed against a polishing pad. As such, a carrier plate may be adapted to apply a greater pressure in a first portion of the topography than in a second portion of the topography when the topography is pressed against a polishing pad. Such an adaptation of a carrier plate may be in addition to the backing film adaptation as described above or may be a completely independent system. In one embodiment, the carrier plate may include a recessed portion. A backing film may include a continuous layer formed across and upon the side of the carrier plate including the recessed region. In alternative embodiment, the backing film may be attached only to a region of the carrier plate adjacent to the recessed region. The lateral dimensions of the recessed portion may be approximately equal to the lateral dimensions of the second portion of the topography. For example, the diameter of the recessed portion may be less than a diameter of the carrier plate by an amount between approximately 2 mm and approximately 20 mm. As such, the diameter of the second portion of the topography may be less than a diameter of the carrier plate by an amount between approximately 2 mm and approximately 20 mm. The depth of the recessed portion may influence the onset of polishing and consequently the polish rate of the second portion of the topography. Accordingly, the depth of the recessed portion may correspond to a thickness variation between the first and second portions of an upper layer of the topography. In this manner, the depth of the recessed portion may vary depending on the design specifications of the device (i.e., an integrated circuit). In particular, the depth of the recessed portion may be optimized such that a substantially planar upper surface of the semiconductor topography may be obtained by a subsequent planarization process.
As previously stated, a method is provided herein in which a portion of an upper layer in a region adjacent to an outer edge of the semiconductor topography is polished at a faster rate than a portion of the upper layer in a region comprising the center of the topography. More specifically, the method may include polishing an upper layer of a semiconductor topography such that an average thickness of the upper layer in a region adjacent to an outer edge of the topography may be less than an average thickness of the upper layer in a region comprising the center of the topography. In one embodiment, the thickness of the upper layer in the region adjacent to the outer edge of the semiconductor topography may increase gradually going inward from the outer edge of the topography. In contrast, the thickness of the upper layer in the region comprising the center of the topography may be substantially uniform subsequent to polishing. In an embodiment, the region adjacent to the outer edge of the semiconductor topography may extend inward from the outer edge by an amount between approximately 1 mm and approximately 10 mm. More specifically, the region adjacent to the outer edge of the topography may extend inward from the outer edge by an amount between approximately 2 mm and approximately 4 mm.
As stated above, the process of polishing an upper layer of a semiconductor topography may include polishing the portion of the upper layer in the region adjacent to an outer edge of the semiconductor topography at a faster rate than a portion of the upper layer in a region comprising the center of the semiconductor topography. For example, the polishing rate of the upper layer in a region adjacent to the outer edge may be between approximately 4,000 angstroms/minute and approximately 7,000 angstroms/minute. In contrast, the polishing rate of the upper layer in the region including the center of the topography may be between approximately 500 angstroms/minute and approximately 1,000 angstroms/minute. As such, the portion of the semiconductor topography polished by the polish step may include the region extending from the outer edge of the semiconductor topography and the region including the center of the topography. However, a greater amount of the topography may be removed in the region extending from the outer edge of the topography than from the region comprising the center of the topography since the polishing rate is so much greater at the edge of the topography. The polishing rate variation across the topography may vary, however, depending on the design specifications of the device. In particular, the polishing rates of the method as described herein may be optimized such that a substantially planar upper surface of the semiconductor topography may be obtained by a subsequent planarization process.
In conjunction with the aforementioned systems, the method as described herein may comprise placing a semiconductor topography upon a carrier plate with a carrier backing film interposed between at least a portion of the wafer and the plate. In one embodiment, the polishing process may include a CMP process. The backing film may comprise, for example, a continuous layer conformably formed across and upon a surface of the plate. The plate may comprise a recessed section such that only a segment of the backing film contacts the semiconductor wafer prior to polishing. The lateral dimensions of the segment may be approximately equal to the lateral dimensions of the region adjacent to the outer edge of the semiconductor topography. Alternatively, the carrier backing film may comprise a ring aligned with an outer portion of the carrier plate. The lateral dimensions of the ring may be approximately equal to the lateral dimensions of the region adjacent to the outer edge of the semiconductor topography. The backing film ring may be replaced with a continuous backing film layer prior to or after a planarizing step, when the polishing and planarizing processes are performed on the same system. Alternatively, the polishing process and subsequent planarizing process may be performed on two separate systems so that the backing film does not have to be changed.
The method may further include a planarizing step conducted before or after the polishing process such that an upper surface of the semiconductor topography is substantially planar. In this manner, the thickness of the upper layer of the semiconductor topography may be approximately the same across the entirety of the semiconductor topography. For example, the thickness variation of the upper layer across the entirety of the semiconductor topography may be less than approximately 700 angstroms. In one embodiment, the thickness variation of the planarized upper layer across the entirety of the semiconductor topography may be less than approximately 350 angstroms. Planarizing may include polishing the semiconductor topography at a substantially different polish rate profile than the polishing step. In particular, the polishing rate of the region adjacent to the outer edge of the semiconductor topography may be slightly slower than the polishing rate of the region comprising the center of the topography. For example, the polish rate of an upper layer in the region including the center of the topography may be between approximately 2500 angstroms/minute and approximately 2700 angstroms/minute. By contrast, the polish rate of the upper layer in the region adjacent to the outer edge of the topography may be between approximately 2000 angstroms/minute and approximately 2500 angstroms/minute.
The polish rate variation across the topography may be due to a number of variables involved in the planarization process. In an embodiment, the planarization step may apply a substantially uniform pressure across the topography to obtain its polish rate profile. In another embodiment, the planarization step may assert a substantially uniform pressure across the topography except in the region adjacent to the outer edge of the topography. In one embodiment, planarizing may include a CMP process. In such an embodiment, the CMP system may not include the modified wafer carrier components as may be used in the polishing step. In other words, the CMP system used for the planarization step may include a CMP system configuration commonly used in semiconductor fabrication. Alternatively, the planarization step may include any process which polishes a region at the outer edge of the topography at a slightly slower rate than a region including the center of the topography.
There may be several advantages to forming a substantially planar upper surface upon a semiconductor topography. For example, a semiconductor device may be formed approximately 4 mm from the outer edge of a semiconductor substrate. The formation of semiconductor devices within such a relatively close vicinity of the outer edge of the substrate may allow for an increase in the number of devices that may be formed upon a substrate. Such an increase in semiconductor device formation upon a substrate may increase manufacturing yield and may reduce production costs per semiconductor device.
A semiconductor topography formed by the method is also contemplated herein. The semiconductor topography may include an upper layer formed upon a lower layer. The average thickness of the upper layer in a region adjacent to an outer edge of the semiconductor topography may be less than an average thickness of the upper layer in a region including a center of the topography. In one embodiment, the thickness of the upper layer in the region adjacent to the outer edge of the semiconductor topography may increase gradually going inward from the outer edge of the topography. The region adjacent to the outer edge may extend laterally from the outer edge of the semiconductor topography by an amount between approximately 1 mm and approximately 10 mm. In one embodiment, the region extending laterally from the outer edge of the semiconductor topography may be between approximately 2 mm and approximately 4 mm. The structure arranged in a region adjacent to an outer edge may include at least a portion of a semiconductor device. Such a semiconductor topography may include, therefore, a semiconductor device arranged in a region approximately 4 mm extending laterally from the outer edge of the semiconductor topography.